1. Technical Field
The present disclosure relates to a sub-65 nm process and, more specifically, to a robust self-aligned process for sub-65 nm current-perpendicular junction pillars.
2. Discussion of the Related Art
Patterning of pillar-shaped structures supporting current-perpendicular-to-thin-film-plane (current-perpendicular) transport, such as spin-valves or magnetic tunnel junction devices, in the sub-65 nm range presents several challenges. For magnetic structures in particular, the materials being patterned may be resistant to mature, high-yield, semiconductor-industry-standard etching techniques such as reactive plasma ion etch. Examples of such materials include nickel (Ni), iron (Fe) and cobalt (Co). For such materials, common approaches now make use of ion beam etching (ion milling), which is prone to materials redeposition along the side walls of the device structure features and related resist and/or mask structures.
More generally, formation of pillar-shaped device structures in sub-65 nm dimension would require either a self-aligned insulation opening process or a separate etch-back-based insulation layer opening process.
Conventional self-aligned insulation opening techniques generally favor tall pillar height (>100 nm, for example) and often favor thick insulator layer for process margin controls. Commonly used self-aligned insulation opening techniques include insulator layer planarization and lift-off. An insulator layer planarization process requires the device structure to be sufficiently tall (for example >100 nm) so as to give enough margin for insulation layer etch stop. Electrical integrity of the insulation would also require a relatively thick insulation layer presence after planarization.
In lift-off process, a relatively tall and laterally narrow sacrificial mask structure is formed, for example using a negative electron beam, resist (NEB). The mask is first used for etching to form the desired device structure. After subsequent coating of an insulator layer, the mask may then be removed, for example, by the use of chemical solvents and physical abrasion such as surface polishing. The result of lift-off is a desired contact hole in the insulator layer.
The lift-off process would also favor a tail sacrificial mask which should foe of similar height or taller than the desired insulator layer thickness. This ensures reliable removal of the sacrificial mask structure after insulation deposition.
In both cases, the mask and/or device structure height is dictated toy the process margin relating to the insulator layer thickness and not the lateral size of the device structure pillar being fabricated. As the lateral size of the device structure pillars shrink to well below 65 nm, this becomes increasingly difficult to engineer, as the lateral dimension of the device structure pillar becomes now much less than its height, or the height of the mask structure.
Alternatively, a separate etch-back-based insulator film opening step may be employed. The etch-back-based insulation opening process would require layer-to-layer-registration accuracies well below the feature size, which in this case means repeated use of expensive high precision slow throughput lithography tools such as an electron-beam writer.
Market pressures on high-technology devices such as integrated circuit and magnetic media fabrication require new technologies offering reduced feature size at a reduced cost. Accordingly, advanced fabrication techniques are desired that can produce features in the sub-65 nm range while minimizing the use of expensive processing steps such as electron beam exposure.
In particular, patterning sub-65 nm current-perpendicular junction devices, for example, magnetic tunnel junctions (MTJ) presents a lithographic challenge due to the lack of ideal volatile chemistry for reliable reactive plasma etching of magnetic materials. Approaches commonly use ion beam etching or ion milling to create the desired patterns. In ion beam etching, a bombardment of inert ions may be used to abrade the surfaces of a material to achieve desired features. Unlike other etch techniques such as in reactive plasma etch where removed materials form volatile gas that may foe pumped away, material removed by ion beam etching remains non-volatile and hence, has a tendency to re-deposit, especially along the sidewalls of the device structure being etched, related resist and/or mask structures. This re-deposition may lead to numerous processing quality control issues such as inter-layer electrical shorting, parasitic magnetic coupling and uncontrolled modification of magnetic boundary conditions.
FIG. 1 shows a sketch illustrating side-wall geometry of a current-perpendicular pillar device structure. Side-wall coating can prove detrimental to the quality of top level electrode contact definition and can interfere with lift-off processing.
The illustration of FIG. 1 shows the effects of sidewall re-deposition. Here, visible sidewalls 24 surround the structure of the device structure pillar. Example device structures of a magnetic tunnel junction include an electrically conducting substrate layer 20, a magnetically fixed layer 21, for example, comprising iron and/or iron-cobalt that is magnetically pinned by an antiferromagnetic layer that could either be part of layer 21 or 20; a magnetic tunnel barrier layer 22, for example, comprising aluminum oxide or magnesium oxide, and a ferromagnetic free layer 23, for example, comprising iron and/or iron-cobalt. The area of the electrically conducting substrate layer 20 that is not covered by the device structure 21-23 forms an exposed surface layer.
One proposed solution to the problem of side-wall coating is to carefully engineer the etch-mask side-wall geometry so as to provide controlled side-wall etch profiles that minimise re-deposition during primary etching. Subsequent ion milling may then be applied at various angles to clean up re-deposition. An example of this approach may be seen in U.S. Pat. No. 6,965,138 which is incorporated by reference herein.
Another proposed solution to the problem of side-wall coating is to develop a careful combination of ion beam incident angles and energies during ion milling. However, this approach is highly dependent on the given feature size and material combination and accordingly, the approach must foe optimised, for each particular application. An example of this approach may be seen in U.S. Patent Application Publication No. 2005/0269238 which is incorporated by reference herein.
However, these methods for controlling side-wall geometry are not easily scalable as mask thickness must be scaled along with lateral feature size. Accomplishing this may foe inconvenient or impractical. Moreover, as the junction feature size is reduced to below the thickness of the mask layer, the ability to control side-wall geometry using these conventional approaches suffers further with the optimum combination of ion mill energy and angles depending on the sensitivity of the materials to be milled and the height and side-wall profile geometry of the mask being used. Accordingly, the search for optimal ion mill conditions may be tedious, may not be easily scalable, may not be easily transferable between different ion mill tools and may not be easily transferable between different materials systems.
Another approach relates to the use of thin hard masks such as diamond-like-carbon (DLC) in combination with a shallow depth ion mill etch. The thin mask layer may reduce the build-up of side-wall re-deposition around the mask layer that could interfere with top level insulator and electrode definition. The thin mask may also facilitate the control of a side wall profile of an etched device structure pillar. This approach relies on a substantial etch rate differential between DLC and common magnetic metal such as Co and Ni in the energy range of approximately 200 eV to approximately 500 eV. This approach may be useful in mitigating problems associated with side-wall profile control and related re-deposition problems. However, this approach generally requires the formation of a separate insulator via openings step or a chemical, mechanical polish or other forms of insulator layer planarization steps. As discussed earlier, these options become increasingly undesirable or impractical as the lateral size of the device structure pillar shrinks below 65 nm or the preferred insulation layer thickness. The formation of the separate insulator via openings requires layer overlay accuracy substantially finer than the minimum feature size. This may be executed using multiple levels of electron-beam lithography which is complex, inefficient and costly. Self-aligned top electrode opening based on planarisation requires sizable device structure junction pillar height to provide an adequate margin for insulator layer etch stop, which could diminish the advantage of a thin mask.